Rate multipliers are well-known to the art, being used in digital adder, subtracter, multiplier, square rooter and e.sup.x function circuits among others. The purpose of the rate multiplier is to produce an output frequency f.sub.out in response to an input frequency f.sub.in, where the ratio between the two is shown in the following equation: EQU f.sub.out = (M/N) f.sub.in
In the prior art N had a constant value for a given rate multiplier, dependent on the number, n, of stages found in the rate multiplier, according to the equation: EQU N = 2.sup.n.
If a rate multiplier had six-stages, for example, N would be 2.sup.6 or 64. Any frequency ratio from 1/64 through 63/64 could be implemented by the rate multiplier by properly selecting M to be 1,2, . . . 62,63 as required. In the prior art M was defined as: EQU M=F.2.sup.5 +E.2.sup.4 +D.2.sup.3 +C.2.sup.2 +B.2.sup.1 +A.2.sup.0
setting rate inputs A through F to 1 or 0 as desired would produce the required M. In any instance, however, the prior art rate multiplier would require N = 2.sup.n inputs at f.sub.in to generate the appropriate f.sub.out. Thus, if f.sub.out was to be half of f.sub.in, M would be set with F = i with A, B, C, D, E equal to .phi., thereby providing 32 outut pulses for each 64 input pulses.
No matter what frequency ratio was sought, 64 input pulses were required by the prior art to produce the proper output frequency.